EUROCOM TN120T Manuel de service télécharger pdf (Page 70)

Schematic Diagrams

B - 18 Clock Generator

B.Schematic Diagrams

Clock Generator

Sheet 17 of 37

Clock Generator

3.3VS

3. 3 V S

1.05VS

3.3VS

C L K_PC IE_I CH # 13

3. 3 V S5,8,9,10,11,12,13,14,15,18,19,20,21,22,23,24,25,29

CLK_MCH_BCLK# 4

C LK_ CP U_BC LK 2

C L K_DREFS S 5

C L K_PC IE_I CH 13

C L K_DREF 5

C L K_DREFS S# 5

C LK_ CP U_BC LK# 2

C L K_DREF# 5

CLK_MCH_BCLK 4

WLAN_CLKREQ# 19,23

C LK_ BSEL02,4

CLK_ICH4814

C LK_ BSEL12,4

C LK_ BSEL22,4

CLK_ICH1414

PM_STP PCI #14

PM_STPCPU#14

PC L K_K BC22

C L K_PW RGD14

IC H _S MBC L K010,11,14

ICH _S MBD AT010,11,14

P C LK _I C H3 313

1.05VS2,3,4,5,7,8,12,15,27

C L K_PC IE_C R 20

C L K_SATA# 12

C L K_PC IE_C R# 2 0

C L K_PC IE_3GPLL# 5

C L K_PC IE_3GPLL 5

C L K_SATA 12

C L K_PC IE_MINI # 19

C L K_PC IE_MINI 19

MCH_CLKREQ# 5

C L K_PC IE_MINI _3 G# 23

C L K_PC IE_MINI _3 G 23

SATA_CLKREQ#14

NEW _C LKR EQ#19

C L K_PC IE_LAN 23

C L K_PC IE_LAN # 23

C L K_PC IE_N EW_CAR D# 19

C L K_PC IE_N EW_CAR D 19

PC L K_TPM19

C LK_ CP U_BC LK#

C L K_DREF SS

C L K_DREF #

C L K_DREF

C L K_PC IE_I CH

CLK_MCH_BCLK

C LK_ CP U_BC LK

C L K_PC IE_I CH #

CLK_MCH_BCLK#

C L K_DREF SS#

C L K_B SEL0

CLK_ICH48

C L K_B SEL1

C L K_B SEL2

CLK_ICH14

PCLK_KBC

PCLK_ICH33

C L K_PC IE_3G PLL

C L K_PC IE_C R

C L K_PC IE_3G PLL#

C L K_PC IE_C R#

C L K_SATA

C L K_SATA#

C L K_PC IE_MINI

C L K_PC IE_MINI #

C L K_PC IE_MINI _3G

C L K_PC IE_MINI _3G#

C L K_PC IE_LAN #

C L K_PC IE_LAN

C L K_PC IE_N EW_CA RD #

C L K_PC IE_N EW_CA RD

XTAL_I N

XTAL_OU T

PCLK_TPM

C411

0.1U_10V_X7R_04

C444

0 .1 U _1 0 V _X 7 R _0 4

R61 2. 2K_04

C412

0.1U_10V_X7R_04

C136

1U_6.3V_04

C422

0 .1 U _1 0 V _X 7 R _0 4

X1 FSX8L_14.318MHz

12

34

L4 HCB1608KF-121T25

R70 10K_04

C125

10U_6.3V_08

R68 33_ 04

C91

10U_6.3V_08

C10 8

1U _ 6. 3 V _ 04

C428

0. 1 U _ 1 0V _X7 R _ 0 4

R40 475_1%_04

C440

0. 1 U _1 0 V _X7 R_ 0 4

C445

0.1U_10V_X7R_04

C431

1U_6.3V_04

C419

1U_6.3V_04

U1

SLG8S P510 T

5

9

61

37

51

53

43

50

54

8

11

7

63

49

62

10

26

48

60

59

42

44

39

3

4

20

55

64

6

1

15

16

23

52

45

46

22

21

30

31

35

34

33

32

18

17

13

14

56

36

12

2

19

29

41

40

27

28

24

25

58

38

47

57

PCI3

VD D48

VD DREF

CPU_STOP#

CP U1

CPU0#

SRC7#/CR#_E

CPU1#

CP U0

GNDPCI

GND48

PCIF5/ITP_EN

SDATA

VD D CP U_IO

REF0/FSLC/EST_SEL

USB_48MHz/FSLA

VD DSRC_ IO 1

NC

X1

X2

GNDSRC3

SRC7/CR#_F

VD D SR C

PCI1/CR#_B

PCI2/TME

VDDPLL3_IO

VD D C PU

SCLK

PCI4/27_Select

PCI0/CR#_A

GN D

VD DPLL 3

GNDS RC1

GNDCPU

VDDSR C_ IO 3

SRC8#/ITP#

SRC2 #/SA TA#

SR C 2/ SATA

SR C9

SRC 9#

SRC10#

SRC 10

SRC11/CR#_H

S R C 1 1# / C R # _G

27 M H z _S S /S R C 1 #/ S E2

27MHz_NonSS/SRC1/SE1

SRC0/DOTT_96

SRC0#/DOTC_96

CK_PWRGD/PD#

VD DSR C _IO 2

VD D _IO

VDDPCI

GND

GNDSRC2

SR C6

SRC 6#

SR C4

SRC 4#

SR C3 /CR# _C

SRC3#/CR#_D

GN D R E F

PCI_STOP#

SRC8/ ITP

F SLB /TEST_MO DE

C168

22P_50V_04

R64 10K_04

R73 10K_04

C435

0.1U_10V_X7R_04

R84 475_1%_04

R76 *10K_ 0 4

R82 475_1%_04

L2 HCB1608KF-121T25

R78 10K_04

R80 *10K_ 0 4

C167

22 P_ 50V_ 04

R31 6 *33_ 04

R75 33_ 04

R41 475_1%_04

R71 33_ 04

C426

0.1U_10V _X7R_04

R74 33_ 04

CLOCK GENERATOR

166 MHz

CK 50 5

BS EL 2

667 MH z0

200 MHz

266 MHz

0

BSEL0

0

40mils

800 MH z

0

FSLB

01

Frequency

BSEL1

Ho st Cl o ck

0

FS LC

11

FSLA

1066 MHz

40mils

PLACE CRYSTAL WIT HIN

500 MILS OF

SLG8SP510T

Layout not e:

Zo=55 Ohm

Zo=55 Ohm

SL Zdiff=100 Ohm

MS Zdiff=95 Ohm

9LPRS365

FS LA

FS LB

FS LC

CR#_A(SATA_CLKREQ#) --> SRC2/2# --> CLK_SATA

CR#_B(NEW_CLKREQ#) --> SRC4/4# --> CLK_PCIE_NEW_CARD

CR#_H(MCH_CLKREQ#) --> SRC10/10# --> CLK_PCIE_3GPLL

CR#_G(WLAN_CLKREQ#) --> SRC9/9# --> CLK_PCIE_MINI

0 = PIN 46 /47 as SRC_ 8

1 = PIN 46 /47 as CPU_ ITP

0 = Pin 13 /14 as DOT9 6, 17/18 as LCD_CLK

1 = Pin 13 /14 as SRC_ 0, 17/18 as 27M/27MSS

Pin-7

Pin-6

RTM875T-606-VD-GR

1 2 ... 65 66 67 68 69 70 71 72 73 74 75 ... 89 90

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